AC82G41SLGQ3 Datasheet, PDF (525/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Functional Description
13 Functional Description
13.1
13.1.1
13.1.2
13.1.3
13.1.4
Host Interface
The (G)MCH supports the Intel^® Core™2 Extreme processor QX9000 series, Intel^®
Core™2 Quad processor Q9000 series, and Intel^® Core™2 Duo processor E8000 and
E7000 series in the LGA775 Land Grid Array Package. The cache line size is 64 bytes.
Source synchronous transfer is used for the address and data signals. The address
signals are double pumped and a new address can be generated every other bus clock.
At 200/267/333MHz bus clock the address signals run at 667MT/s. The data is quad
pumped and an entire 64B cache line can be transferred in two bus clocks. At 200/266/
333 MHz bus clock, the data signals run at 800/1066/1333 MT/s for a maximum
bandwidth of 6.4/8.5/10.6 GB/s.
FSB IOQ Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions.
FSB OOQ Depth
The (G)MCH supports only one outstanding deferred transaction on the FSB.
FSB GTL+ Termination
The (G)MCH integrates GTL+ termination resistors on die.
FSB Dynamic Bus Inversion
The (G)MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving
data from the processor. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the worst-case power
consumption of the (G)MCH. FSB_DINVB_[3:0] indicate if the corresponding 16 bits of
data are inverted on the bus for each quad pumped data phase:
FSB_DINVB_[3:0]
FSB_DINVB_0
FSB_DINVB_1
FSB_DINVB_2
FSB_DINVB_3
Data Bits
FSB_DB_[15:0]#
FSB_DB_[31:16]#
FSB_DB_[47:32]#
FSB_DB_[63:48]#
Whenever the processor or the (G)MCH drives data, each 16-bit segment is analyzed.
If more than 8 of the 16 signals would normally be driven low on the bus, the
corresponding FSB_DINVB signal will be asserted, and the data will be inverted prior to
being driven on the bus. Whenever the processor or the (G)MCH receives data, it
monitors FSB_DINVB_[3:0] to determine if the corresponding data segment should be
inverted.
Datasheet
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