AC82G41SLGQ3 Datasheet, PDF (469/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.2.7
CCMD_REG—Context Command Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
28-2Fh
0000000000000000h
RO, R/W, W
64 bits
This register is used to manage context cache. The act of writing the uppermost byte of
the CCMD_REG with ICC field set causes the hardware to perform the context-cache
invalidation.
Bit
Access
Default
Value
RST/PWR
Description
Invalidate Context-Cache (ICC): Software requests
invalidation of context-cache by setting this field. Software
must also set the requested invalidation granularity by
programming the CIRG field.
Software must read back and check the ICC field to be
clear to confirm the invalidation is complete. Software
must not update this register when this field is set.
Hardware clears the ICC field to indicate the invalidation
request is complete. Hardware also indicates the
granularity at which the invalidation operation was
performed through the CAIG field. Software must not
submit another invalidation request through this register
while the ICC field is set.
63
R/W
0h
Core
Software must submit a context cache invalidation request
through this field only when there are no invalidation
requests pending at this DMA-remapping hardware unit.
Refer to Section 9 for software programming
requirements.
Since information from the context-cache may be used by
hardware to tag IOTLB entries, software must perform
domain-selective (or global) invalidation of IOTLB after the
context cache invalidation has completed.
Hardware implementations reporting write-buffer flushing
requirement (RWBF=1 in Capability register) must
implicitly perform a write buffer flushing before reporting
invalidation complete to software through the ICC field.
Datasheet
469