AC82G41SLGQ3 Datasheet, PDF (5/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

5.1.12 PXPEPBAR—PCI Express Egress Port Base Address...................................... 93
5.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base ............................ 94
5.1.14 GGC—GMCH Graphics Control Register (Intel^® 82Q45, 82Q43, 82B43, 82G45,
82G43, 82G41 GMCH Only) ..................................................................... 95
5.1.15 DEVEN—Device Enable............................................................................ 97
5.1.16 PCIEXBAR—PCI Express Register Range Base Address................................. 99
5.1.17 DMIBAR—Root Complex Register Range Base Address............................... 101
5.1.18 PAM0—Programmable Attribute Map 0 .................................................... 102
5.1.19 PAM1—Programmable Attribute Map 1 .................................................... 103
5.1.20 PAM2—Programmable Attribute Map 2 .................................................... 104
5.1.21 PAM3—Programmable Attribute Map 3 .................................................... 105
5.1.22 PAM4—Programmable Attribute Map 4 .................................................... 106
5.1.23 PAM5—Programmable Attribute Map 5 .................................................... 107
5.1.24 PAM6—Programmable Attribute Map 6 .................................................... 108
5.1.25 LAC—Legacy Access Control .................................................................. 109
5.1.26 REMAPBASE—Remap Base Address Register ............................................ 111
5.1.27 REMAPLIMIT—Remap Limit Address Register............................................ 111
5.1.28 SMRAM—System Management RAM Control ............................................. 112
5.1.29 ESMRAMC—Extended System Management RAM Control............................ 113
5.1.30 TOM—Top of Memory............................................................................ 114
5.1.31 TOUUD—Top of Upper Usable DRAM ....................................................... 115
5.1.32 GBSM—Graphics Base of Stolen Memory (Intel^® 82Q45, 82Q43, 82B43, 82G45,
82G43, 82G41 GMCH Only) ................................................................... 116
5.1.33 BGSM—Base of GTT stolen Memory (Intel^® 82Q45, 82Q43, 82B43, 82G45,
82G43, 82G41 GMCH Only) ................................................................... 116
5.1.34 TSEGMB—TSEG Memory Base ................................................................ 117
5.1.35 TOLUD—Top of Low Usable DRAM........................................................... 117
5.1.36 ERRSTS—Error Status ........................................................................... 118
5.1.37 ERRCMD—Error Command..................................................................... 120
5.1.38 SMICMD—SMI Command....................................................................... 121
5.1.39 SKPD—Scratchpad Data ........................................................................ 122
5.1.40 CAPID0—Capability Identifier ................................................................. 122
5.2 MCHBAR ........................................................................................................ 123
5.2.1 CHDECMISC—Channel Decode Miscellaneous ........................................... 125
5.2.2 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ............................... 126
5.2.3 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 ............................... 128
5.2.4 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 ............................... 128
5.2.5 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 ............................... 129
5.2.6 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute ........................................ 130
5.2.7 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute ........................................ 131
5.2.8 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG ............................................. 131
5.2.9 C0CYCTRKACT—Channel 0 CYCTRK ACT .................................................. 132
5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR.................................................... 133
5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ ................................................. 134
5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR............................................... 135
5.2.13 C0CKECTRL—Channel 0 CKE Control ....................................................... 135
5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control ....................................... 137
5.2.15 C0ODTCTRL—Channel 0 ODT Control ...................................................... 139
5.2.16 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ............................... 139
5.2.17 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ............................... 140
5.2.18 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 ............................... 140
5.2.19 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes....................................... 141
5.2.20 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes....................................... 141
5.2.21 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG ............................................. 142
5.2.22 C1CYCTRKACT—Channel 1 CYCTRK ACT .................................................. 143
Datasheet
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