AC82G41SLGQ3 Datasheet, PDF (218/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.55
PEGLC—PCI Express-G Legacy Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
EC-EFh
00000000h
RO, R/W
32 bits
This register controls functionality that is needed by Legacy (non-PCI Express aware)
operating systems during run time.
Bit
31:3
2
1
0
Access
RO
R/W
R/W
R/W
Default
Value
00000000h
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Reserved
PME GPE Enable (PMEGPE):
0 = Do not generate GPE PME message when PME is
received.
1 = Generate a GPE PME message when PME is received
(Assert_PMEGPE and Deassert_PMEGPE messages on
DMI). This enables the MCH to support PMEs on the
PEG port under legacy OSs.
Hot-Plug GPE Enable (HPGPE):
0 = Do not generate GPE Hot-Plug message when Hot-Plug
event is received.
1 = Generate a GPE Hot-Plug message when Hot-Plug
Event is received (Assert_HPGPE and Deassert_HPGPE
messages on DMI). This enables the MCH to support
Hot-Plug on the PEG port under legacy OSs.
General Message GPE Enable (GENGPE):
0 = Do not forward received GPE assert/deassert
messages.
1 = Forward received GPE assert/deassert messages.
These general GPE message can be received via the
PEG port from an external Intel device (i.e., PxH) and
will be subsequently forwarded to the ICH (via
Assert_GPE and Deassert_GPE messages on DMI). For
example, PxH might send this message if a PCI
Express device is hot plugged into a PxH downstream
port.
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Datasheet