AC82G41SLGQ3 Datasheet, PDF (600/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Testability
The CL_PWROK pin provides hardware reset to the TAP, so it must be driven low at
power up to ensure clean reset to the TAP. This pin must be driven high to indicate that
power is valid, which also allows the TAP to come out of reset.
CL_RSTB must be high for the specified time, for fuses to be loaded and valid before
PWROK is asserted.
The PWROK pin must be driven high in order to indicate that power is valid. It also
latches the BSCANTEST strap.
The RSTINB pin must be initially active (low) then de-asserted (high) so that the I/O
buffers will operate correctly.
Clocking of the HPL_CLKINN/P and EXP_CLKN/P pins is required to initialize internal
registers including those that set default buffer compensation values. Clock frequency
is not critical due to PLL bypass mode forced when bscantest strap is asserted.
The JTAG_TMS pin should be held high before asserting MEPWROK (CL_PWROK), and
held high for at least 5 JTAG_TCK cycles to ensure that the TAP exits the Test-Logic-
Reset state at the expected time once TMS goes low. Note that JTAG_TMS has an
internal pullup.
16.1.1
Table 55.
TAP Instructions and Opcodes
The TAP controller supports the JTAG instructions as listed in Table 55. The instruction
register length is 4 bits.
Supported TAP Instructions
Opcode
(binary)
0000b
0001b
Instruction
EXTEST
SAMPLE/
PRELOAD (SAMPRE)
0011b
IDCODE
0100b
0101b
0110b
1111b
others
CLAMP
EXTEST_TOGGLE
HIGHZ
BYPASS
Reserved
Selected Test Data
Register
Boundary-scan
Boundary-scan
Device Identification
(value: 0x04105013)
Bypass
Boundary-scan
Bypass
Bypass
TDR Length
485
485
32
1
485
1
1
16.1.2
TAP interface and timings.
The (G)MCH uses 4 dedicated pins to access the Test Access Port (TAP), and the port
timings are shown in Figure 23.
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Datasheet