AC82G41SLGQ3 Datasheet, PDF (333/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.2.9
HECI_MBAR— HECI MMIO Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
10-17h
0000000000000004h
R/W, RO
64 bits
This register allocates space for the HECI memory mapped registers.
Bit
63:4
3
2:1
0
Access
R/W
RO
RO
RO
Default
Value
000000000
000000h
0b
10b
0b
RST/PWR
Description
Core
Core
Core
Core
Base Address (BA): Base address of register memory
space.
Prefetchable (PF): This bit indicates that this range is not
pre-fetchable
Type (TP): This field indicates that this range can be
mapped anywhere in 32-bit address space
Resource Type Indicator (RTE): This bit indicates a
request for register memory space.
10.2.10 SS— Sub System Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/PCI
2C-2Fh
00000000h
R/WO
32 bits
Bit
Access
31:16
R/WO
15:0
R/WO
Default
Value
0000h
0000h
RST/PWR
Description
Core
Core
Subsystem ID (SSID): This field indicates the sub-
system identifier. This field should be programmed by BIOS
during boot-up. Once written, this register becomes Read
Only. This field can only be cleared by PLTRST#.
Subsystem Vendor ID (SSVID): This field indicates the
sub-system vendor identifier. This field should be
programmed by BIOS during boot-up. Once written, this
register becomes Read Only. This field can only be cleared
by PLTRST#.
Datasheet
333