AC82G41SLGQ3 Datasheet, PDF (513/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.3.16 PLMLIMIT_REG—Protected Low Memory Limit Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/GFXVTBAR
6C-6Fh
00000000h
R/W, RO
32 bits
This register is used to setup the limit address of DMA protected low-memory region.
This register must be setup before enabling protected memory through PMEN_REG,
and must not be updated when protected memory regions are enabled.
When LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO).
When LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated as
R/W).
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as 0 in the Capability register). The alignment of
the protected low memory region limit depends on the number of reserved bits (N) of
this register. Software may determine the value of N by writing all 1s to this register,
and finding most significant zero bit position with 0 in the value read back from the
register. Bits N:0 of the limit register is decoded by hardware as all 1s.
The Protected low-memory base & limit registers functions as follows:
• Programming the protected low-memory base and limit registers with the same
value in bits 31:(N+1) specifies a protected low-memory region of size 2(N+1)
bytes.
• Programming the protected low-memory limit register with a value less than the
protected low-memory base register disables the protected low-memory region.
Bit
31:21
20:0
Access
R/W
RO
Default
Value
000h
000000h
RST/PWR
Description
Core
Core
Protected Low-Memory Limit (PLML): This field
specifies the last host physical address of the DMA
protected low-memory region in system memory.
Reserved
Datasheet
513