AC82G41SLGQ3 Datasheet, PDF (93/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.11
CAPPTR—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
34h
E0h
RO
8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
Bit
Access
Default
Value
7:0
RO
E0h
RST/
PWR
Core
Description
Capabilities Pointer (CAPPTR): This field is a pointer to
the offset of the first capability ID register block. In this
case the first capability is the product-specific Capability
Identifier (CAPID0).
5.1.12
Note:
PXPEPBAR—PCI Express Egress Port Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
40-47h
0000000000000000h
RO, R/W/L
64 bits
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4 KB window that can be addressed. The 4 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the EGRESS port MMIO configuration space is disabled and must be
enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0]
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
63:36
Access
RO
Default
Value
0000000h
35:12
R/W/L
000000h
11:1
0
RO
R/W/L
000h
0b
RST/
PWR
Core
Core
Core
Core
Description
Reserved
PCI Express Egress Port MMIO Base Address
(PXPEPBAR): This field corresponds to bits 35:12 of the
base address PCI Express Egress Port MMIO configuration
space. BIOS will program this register resulting in a base
address for a 4 KB block of contiguous memory address
space. This register ensures that a naturally aligned 4 KB
space is allocated within the first 6 4GB of addressable
memory space. System Software uses this base address to
program the (G)MCH MMIO register set.
Reserved
PXPEPBAR Enable (PXPEPBAREN):
0 = PXPEPBAR is disabled and does not claim any memory
1 = PXPEPBAR memory mapped accesses are claimed and
decoded appropriately
Datasheet
93