AC82G41SLGQ3 Datasheet, PDF (101/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.17
Note:
DMIBAR—Root Complex Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
68-6Fh
0000000000000000h
RO, R/W/L
64 bits
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the (G)MCH. There is no physical memory within this 4 KB window that
can be addressed. The 4 KB reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. On reset, the Root Complex configuration space is
disabled and must be enabled by writing a 1 to DMIBAREN [Dev 0, offset 68h, bit 0].
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
63:36
35:12
11:1
0
Access
RO
R/W/L
RO
R/W/L
Default
Value
0000000h
000000h
000h
0b
RST/PWR
Description
Core
Core
Core
Core
Reserved
DMI Base Address (DMIBAR): This field corresponds to
bits 35:12 of the base address DMI configuration space.
BIOS will program this register resulting in a base address
for a 4 KB block of contiguous memory address space. This
register ensures that a naturally aligned 4 KB space is
allocated within the first 64 GB of addressable memory
space. System Software uses this base address to program
the DMI register set.
Reserved
DMIBAR Enable (DMIBAREN):
0 = DMIBAR is disabled and does not claim any memory
1 = DMIBAR memory mapped accesses are claimed and
decoded appropriately
Datasheet
101