AC82G41SLGQ3 Datasheet, PDF (197/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.30
MC—Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
92-93h
0000h
RO, R/W
16 bits
System software can modify bits in this register, but the device is prohibited from
modifying bits.
If the device writes the same message multiple times, only one of those messages is
ensured to be serviced. If all of them must be serviced, the device must not generate
the same message again until the driver services the earlier one.
Bit
15:8
7
6:4
3:1
0
Access
RO
RO
R/W
RO
R/W
Default
Value
00h
0b
000b
000b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Reserved
64-bit Address Capable (64AC): Hardwired to 0 to
indicate that the function does not implement the upper
32 bits of the Message Address register and is incapable of
generating a 64-bit memory address.
This may need to change in future implementations when
addressable system memory exceeds the 32b/4 GB limit.
Multiple Message Enable (MME): System software
programs this field to indicate the actual number of
messages allocated to this device. This number will be
equal to or less than the number actually requested.
The encoding is the same as for the MMC field below.
Multiple Message Capable (MMC): System software
reads this field to determine the number of messages
being requested by this device.
000 = 1
All other encodings are reserved.
MSI Enable (MSIEN): This bit controls the ability of this
device to generate MSIs.
0 = MSI will not be generated.
1 = MSI will be generated when we receive PME or
HotPlug messages. INTA will not be generated and
INTA Status (PCISTS1[3]) will not be set.
Datasheet
197