AC82G41SLGQ3 Datasheet, PDF (291/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
Bit
Access
Default
Value
RST/
PWR
Description
Internal Graphics Engine Function 1 (D2F1EN):
0 = Bus 0, Device 2, Function 1 is disabled and hidden
1 = Bus 0, Device 2, Function 1 is enabled and visible
If Device 2, Function 0 is disabled and hidden, then Device 2,
4
RO
1b
Core _{Function 1 is also disabled and hidden independent of the state}
of this bit.
If this component is not capable of Dual Independent Display
(CAPID0[78] = 1), then this bit is hardwired to 0b to hide Device
2, Function 1.
Internal Graphics Engine Function 0 (D2F0EN):
0 = Bus 0, Device 2, Function 0 is disabled and hidden
3
RO
1b
Core ^{1 = Bus 0, Device 2, Function 0 is enabled and visible}
If this GMCH does not have internal graphics capability
(CAPID0[46] = 1), then Device 2, Function 0 is disabled and
hidden independent of the state of this bit.
2
RO
0b
Core Reserved
PCI Express Port (D1EN):
0 = Bus 0, Device 1, Function 0 is disabled and hidden.
1 = Bus 0, Device 1, Function 0 is enabled and visible.
Default value is determined by the device capabilities (see
1
RO
1b
Core _{CAPID0[44]), SDVO Presence hardware strap and the sDVO/}
PCIe Concurrent hardware strap. Device 1 is Disabled on Reset if
the SDVO Presence strap was sampled high, and the sDVO/PCIe
Concurrent strap was sampled low at the last assertion of
PWROK, and is enabled by default otherwise.
0
RO
1b
Core
Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be
disabled and is therefore hardwired to 1.
Datasheet
291