AC82G41SLGQ3 Datasheet, PDF (131/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.7
C0DRA23—Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
20A-20Bh
0000h
R/W/L
16 bits
See the C0DRA01 register for detailed descriptions.
Bit
15:8
7:0
5.2.8
Access
R/W/L
R/W/L
Default
Value
00h
00h
RST/PWR
Description
Core
Core
Channel 0 DRAM Rank-3 Attributes (C0DRA3): This
register defines DRAM pagesize/number-of-banks for
rank3 for given channel. See Table 12.
This register is locked by ME stolen Memory lock.
Channel 0 DRAM Rank-2 Attributes (C0DRA2): This
register defines DRAM pagesize/number-of-banks for
rank2 for given channel. See Table 12.
This register is locked by ME stolen Memory lock.
C0CYCTRKPCHG—Channel 0 CYCTRK PCHG
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
250-251h
0000h
R/W, RO
16 bits
This register is for Channel 0 CYCTRK Precharge control.
Bit
15:11
Access
RO
10:6
R/W
5:2
R/W
1:0
R/W
Default
Value
00000b
00000b
0000b
00b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Write To PRE Delayed (C0sd_cr_wr_pchg): This
configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the WRITE and PRE
commands to the same rank-bank.This field corresponds to
tWR in the DDR Specification.
READ To PRE Delayed (C0sd_cr_rd_pchg): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the READ and PRE commands to the same rank-
bank
PRE To PRE Delayed (C0sd_cr_pchg_pchg): This field
indicates the minimum allowed spacing (in DRAM clocks)
between two PRE commands to the same rank.
Datasheet
131