AC82G41SLGQ3 Datasheet, PDF (72/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

System Address Map
3.9
3.10
GTT Fetches are always decoded (at fetch time) to ensure not in SMM (actually,
anything above base of TSEG or 640 KB–1 MB). Thus, they will be invalid and go to
address 000C_0000h, but that is not specific to PCI Express or DMI; it applies to
processor or internal graphics engines. Also, since the GMADR snoop would not be
directly to the SMM space, there wouldn’t be a writeback to SMM. In fact, the writeback
would also be invalid (because it uses the same translation) and go to address
000C_0000h.
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
“shadowed” into (G)MCH DRAM memory. Typically this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as a read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. Processor bus transactions are
routed accordingly.
I/O Address Space
The (G)MCH does not support the existence of any other I/O devices beside itself on
the processor bus. The (G)MCH generates either DMI Interface or PCI Express bus
cycles for all processor I/O accesses that it does not claim. Within the host bridge, the
(G)MCH contains two internal registers in the processor I/O space, Configuration
Address Register (CONFIG_ADDRESS) and the Configuration Data Register
(CONFIG_DATA). These locations are used to implement configuration space access
mechanism.
The processor allows 64 K+3 bytes to be addressed within the I/O space. The (G)MCH
propagates the processor I/O address without any translation on to the destination bus
and therefore provides addressability for 64K+3 byte locations. Note that the upper 3
locations can be accessed only during I/O address wrap-around when processor bus
HAB_16 address signal is asserted. HAB_16 is asserted on the processor bus whenever
an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. HAB_16 is
also asserted when an I/O access is made to 2 bytes from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are
consumed by the internal graphics device if it is enabled. The mechanisms for internal
graphics I/O decode and the associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI Interface bus unless they fall within the PCI Express I/O address
range as defined by the mechanisms explained below. I/O writes are NOT posted.
Memory writes to ICH or PCI Express are posted. The PCICMD1 register can disable the
routing of I/O cycles to the PCI Express.
The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with an UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur, the
request will route as a read to Memory address 000C_0000h so a completion is
naturally generated (whether the original request was a read or write). The transaction
will complete with an UR completion status.
I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries are issued from
the processor as 1 transaction. The (G)MCH will break this into 2 separate transactions.
I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries are assumed
to be split into 2 transactions by the processor.
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