AC82G41SLGQ3 Datasheet, PDF (363/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.3
IDEERD0—IDE Error Register DEV0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
1h
00h
R/W/V
8 bits
Reset: Host system reset or D3->D0 transition
This register implements the Error register of the command block of the IDE function.
This register is read only by the HOST interface when DEV = 0 (master device).
When the HOST writes the same address it writes to the Features register.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Error Data (IDEED): Drive reflects its error/
diagnostic code to the host via this register at different
times.
10.6.4
IDEFR—IDE Features Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
1h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Feature register of the command block of the IDE
function. This register can be written only by the Host.
When the HOST reads the same address, it reads the Error register of Device 0 or
Device 1 depending on the device_select bit (bit 4 of the drive/head register).
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Feature Data (IDEFD): IDE drive specific data
written by the Host
Datasheet
363