AC82G41SLGQ3 Datasheet, PDF (388/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
Bit
Access
Default
Value
RST/PWR
Description
Bus Master Enable (BME): This bit controls the KT
function's ability to act as a master for data transfers. This
2
R/W
0b
Core
bit does not impact the generation of completions for split
transaction commands. For KT, the only bus mastering
activity is MSI generation.
1
R/W
0b
Core
Memory Space Enable (MSE): This bit controls Access to
the PT function's target memory space.
0
R/W
0b
Core
I/O Space enable (IOSE): This bit controls access to the
PT function's target I/O space.
10.9.3
STS—Device Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
6-7h
00B0h
RO
16 bits
This register is used by the function to reflect its PCI status to the host for the
functionality that it implements
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
00b
0b
1b
0b
1b
1b
0b
000b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Detected Parity Error (DPE): No parity error on its
interface.
Signaled System Error (SSE): The PT function will never
generate an SERR#.
Received Master-Abort Status (RMA): Reserved
Received Target-Abort Status (RTA): Reserved
Signaled Target-Abort Status (STA): The PT Function
will never generate a target abort. Reserved
DEVSEL# Timing Status (DEVT): This field controls the
device select time for the PT function's PCI interface.
Master Data Parity Error Detected) (DPD): PT function
(IDER), as a master, does not detect a parity error. Other
PT function is not a master and hence this bit is reserved
also.
Fast back to back capable: Reserved
Reserved
66MHz capable: Reserved
Capabilities List (CL): This bit indicates that there is a
capabilities pointer implemented in the device.
Interrupt Status (IS): This bit reflects the state of the
interrupt in the function. Setting of the Interrupt Disable
bit to 1 has no affect on this bit. Only when this bit is a 1
and ID bit is 0 is the INTB interrupt asserted to the Host.
Reserved
388
Datasheet