AC82G41SLGQ3 Datasheet, PDF (406/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.10.10 KTLSR—KT Line Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
5h
00h
RO, RO/CR
8 bits
Reset: Host system reset or D3->D0 transition
This register provides status information of the data transfer to the Host. Error
indication, etc. are provided by the HW/FW to the host via this register.
Bit
Access
Default
Value
RST/PWR
Description
7
RO
0b
6
RO
0b
5
RO
0b
4
RO/CR
0b
3
RO
0b
2
RO
0b
1
RO/CR
0b
0
RO
0b
Core
Core
Core
Core
Core
Core
Core
Core
RX FIFO Error (RXFER): This bit is cleared in non FIFO
mode. This bit is connected to BI bit in FIFO mode.
Transmit Shift Register Empty (TEMT): This bit is
connected by HW to bit 5 (THRE) of this register.
Transmit Holding Register Empty (THRE): This bit is
always set when the mode (FIFO/Non-FIFO) is changed by
the Host. This bit is active only when the THR operation is
enabled by the FW. This bit has acts differently in the
different modes:
Non FIFO: This bit is cleared by hardware when the Host
writes to the THR registers and set by hardware when the
FW reads the THR register.
FIFO mode: This bit is set by hardware when the THR
FIFO is empty, and cleared by hardware when the THR
FIFO is not empty.
This bit is reset on Host system reset or D3->D0 transition.
Break Interrupt (BI): This bit is cleared by hardware
when the LSR register is being read by the Host.
This bit is set by hardware in two cases:
• In FIFO mode the FW sets the BI bit by setting the SBI
bit in the KTRIVR register (See KT AUX registers)
• In non-FIFO mode the FW sets the BI bit by setting the
BIA bit in the KTRxBR register (see KT AUX registers)
Framing Error (FE): This bit is not implemented
Parity Error (PE): This bit is not implemented
Overrun Error (OE): This bit is cleared by hardware when
the LSR register is being read by the Host. The FW typically
sets this bit, but it is cleared by hardware when the host
reads the LSR.
Data Ready (DR):
Non-FIFO Mode: This bit is set when the FW writes to the
RBR register and cleared by hardware when the RBR
register is being Read by the Host.
FIFO Mode: This bit is set by hardware when the RBR
FIFO is not empty and cleared by hardware when the RBR
FIFO is empty.
This bit is reset on Host System Reset or D3->D0
transition.
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Datasheet