AC82G41SLGQ3 Datasheet, PDF (91/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.6
CC—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
9-Bh
060000h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
Bit
23:16
15:8
7:0
5.1.7
Access
RO
RO
RO
Default
Value
06h
00h
00h
RST/PWR
Description
Core
Core
Core
Base Class Code (BCC): This is an 8-bit value that
indicates the base class code for the (G)MCH.
06h = Bridge device.
Sub-Class Code (SUBCC): This is an 8-bit value that
indicates the category of Bridge into which the (G)MCH
falls.
00h = Host Bridge.
Programming Interface (PI): This is an 8-bit value that
indicates the programming interface of this device. This
value does not specify a particular register set layout and
provides no practical use for this device.
MLT—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
Dh
00h
RO
8 bits
Device 0 in the (G)MCH is not a PCI master. Therefore, this register is not
implemented.
Bit
Access
Default
Value
RST/PWR
7:0
RO
00h
Core
Reserved
Description
Datasheet
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