AC82G41SLGQ3 Datasheet, PDF (275/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9 Integrated Graphics Registers
(Device 2) (Intel^® 82Q45,
82Q43, 82B43, 82G45, 82G43,
82G41 GMCH Only)
9.1
Integrated Graphics Registers (D2:F0)
Note:
Table 15.
Device 2 contains registers for the internal graphics functions. Table 15 lists the PCI
configuration registers in order of ascending offset address.
Function 0 can be VGA compatible or not. This is selected through bit 1 of GGC register
(Device 0, offset 52h).
The following sections describe Device 2 PCI configuration registers only.
Integrated Graphics Register Address Map (D2:F0)
Address
Offset
0–1h
Register
Symbol
VID2
Register Name
Vendor Identification
2–3h
DID2
Device Identification
4–5h
6–7h
PCICMD2
PCISTS2
PCI Command
PCI Status
8h
RID2
Revision Identification
9–Bh
Ch
Dh
Eh
10–17h
CC
Class Code
CLS
Cache Line Size
MLT2
Master Latency Timer
HDR2
Header Type
GTTMMADR
Graphics Translation Table, Memory
Mapped Range Address
18–1Fh
GMADR Graphics Memory Range Address
20–23h
2C–2Dh
2E–2Fh
30–33h
34h
3Ch
3Dh
3Eh
IOBAR
SVID2
SID2
ROMADR
CAPPOINT
INTRLINE
INTRPIN
MINGNT
I/O Base Address
Subsystem Vendor Identification
Subsystem Identification
Video BIOS ROM Base Address
Capabilities Pointer
Interrupt Line
Interrupt Pin
Minimum Grant
Default
Value
8086h
see register
description
0000h
0090h
see register
description
030000h
00h
00h
80h
000000000
0000004h
000000000
000000Ch
00000001h
0000h
0000h
00000000h
90h
00h
01h
00h
Access
RO
RO
RO, R/W
RO
RO
RO
RO
RO
RO
R/W, RO
R/W, RO,
|R/W/L
RO, R/W
R/WO
R/WO
RO
RO
R/W
RO
RO
Datasheet
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