AC82G41SLGQ3 Datasheet, PDF (137/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.14
C0REFRCTRL—Channel 0 DRAM Refresh Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
269-26Eh
241830000C30h
R/W, RO
48 bits
This register provides settings to configure the DRAM refresh controller.
Bit
47
46:44
Access
RO
R/W
43:38
R/W
37:32
R/W
31:27
R/W
26
R/W
25
R/W
24
R/W
23
R/W
22
R/W
Default
Value
0b
010b
010000b
011000b
00110b
0b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Reserved
Initial Refresh Count (sd0_cr_init_refrcnt): This field
specifies the initial refresh count value.
Direct Rcomp Quiet Window (DIRQUIET): This
configuration setting indicates the amount of refresh_tick
events to wait before the service of rcomp request in non-
default mode of independent rank refresh.
Indirect Rcomp Quiet Window (INDIRQUIET): This
configuration setting indicates the amount of refresh_tick
events to wait before the service of rcomp request in non-
default mode of independent rank refresh.
Rcomp Wait (RCOMPWAIT): This configuration setting
indicates the amount of refresh_tick events to wait before
the service of rcomp request in non-default mode of
independent rank refresh.
ZQCAL Enable (ZQCALEN): This bit enables the DRAM
controller to issue ZQCAL S command periodically.
Refresh Counter Enable (REFCNTEN): This bit is used
to enable the refresh counter to count during times that
DRAM is not in self-refresh, but refreshes are not enabled.
Such a condition may occur due to need to reprogram
DIMMs following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e., there is
no mode where Refresh is enabled but the counter does
not run). So, along with bit 23 REFEN, the modes are:
REFEN:REFCNTEN Description
0:0
Normal refresh disable
0:1
Refresh disabled, but counter is
accumulating refreshes.
1:X
Normal refresh enable
All Rank Refresh (ALLRKREF): This bit enables (by
default) that all the ranks are refreshed in a staggered/
atomic fashion. If set, the ranks are refreshed in an
independent fashion.
Refresh Enable (REFEN):
0 = Disabled
1 = Enabled
DDR Initialization Done (INITDONE): This bit indicates
that DDR initialization is complete.
Datasheet
137