AC82G41SLGQ3 Datasheet, PDF (251/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.29
MSI_CAPID—Message Signaled Interrupts
Capability ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
90–91h
A005h
RO
16 bits
When a device supports MSI, it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address.
Bit
15:8
7:0
Access
RO
RO
Default
Value
A0h
05h
RST/
PWR
Core
Core
Description
Pointer to Next Capability (PNC): This field contains a pointer to
the next item in the capabilities list which is the PCI Express
capability.
Capability ID (CID): Value of 05h identifies this linked list item
(capability structure) as being for MSI registers.
8.30
MC—Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
92–93h
0000h
RW, RO
16 bits
System software can modify bits in this register, but the device is prohibited from doing
so.
If the device writes the same message multiple times, only one of those messages is
guaranteed to be serviced. If all of them must be serviced, the device must not
generate the same message again until the driver services the earlier one.
Bit
15:8
7
6:4
3:1
0
Access
RO
RO
RW
RO
RW
Default
Value
00h
0b
000b
000b
0b
RST/
PWR
Core
Core
Core
Core
Core
Description
Reserved
64-bit Address Capable (64AC): Hardwired to 0 to indicate that
the function does not implement the upper 32 bits of the Message
Address register and is incapable of generating a 64-bit memory
address.
Multiple Message Enable (MME): System software programs this
field to indicate the actual number of messages allocated to this
device. This number will be equal to or less than the number actually
requested.
The encoding is the same as for the MMC field below.
Multiple Message Capable (MMC): System software reads this
field to determine the number of messages being requested by this
device. The value of 000b equates to 1 message requested.
000 = 1 message requested
All other encodings are reserved.
MSI Enable (MSIEN): Controls the ability of this device to generate
MSIs.
0 = MSI will not be generated.
1 = MSI will be generated when we receive PME messages. INTA will
not be generated and INTA Status (PCISTS1[3]) will not be set.
Datasheet
251