AC82G41SLGQ3 Datasheet, PDF (98/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
Access
Default
Value
6
R/W/L
1b
5
RO
0b
4
(82Q45,
82Q43, 82B43,
82G45, 82G43,
R/W/L
1b
82G41 GMCH
Only)
4
(82P45, 82P43 R/W/L
1b
MCH Only)
3
(82Q45,
82Q43, 82B43,
82G45, 82G43,
R/W/L
1b
82G41 GMCH
Only)
3
(82P45, 82P43 ^R/W/L
1b
Only)
2
RO
0b
1
R/W/L
1b
0
RO
1b
RST/
PWR
Core
Core
Core
Description
EP Function 0 (D3F0EN):
0 = Bus 0, Device 3, Function 0 is disabled and hidden
1 = Bus 0, Device 3, Function 0 is enabled and visible.
Reserved
Internal Graphics Engine Function 1 (D2F1EN):
0 = Bus 0, Device 2, Function 1 is disabled and hidden
1 = Bus 0, Device 2, Function 1 is enabled and visible
If Device 2, Function 0 is disabled and hidden, then Device
2, Function 1 is also disabled and hidden independent of
the state of this bit.
If this component is not capable of Dual Independent
Display (CAPID0[78] = 1), then this bit is hardwired to 0b
to hide Device 2, Function 1.
Core Reserved
Core
Internal Graphics Engine Function 0 (D2F0EN):
0 = Bus 0, Device 2, Function 0 is disabled and hidden
1 = Bus 0, Device 2, Function 0 is enabled and visible
If this GMCH does not have internal graphics capability
(CAPID0[46] = 1), then Device 2, Function 0 is disabled
and hidden independent of the state of this bit.
Core Reserved
Core
Core
Core
Reserved
PCI Express Port (D1EN):
0 = Bus 0, Device 1, Function 0 is disabled and hidden.
1 = Bus 0, Device 1, Function 0 is enabled and visible.
Default value is determined by the device capabilities (see
CAPID0 [44]), SDVO Presence hardware strap and the
sDVO/PCIe Concurrent hardware strap. Device 1 is
Disabled on Reset if the SDVO Presence strap was sampled
high, and the sDVO/PCIe Concurrent strap was sampled
low at the last assertion of PWROK, and is enabled by
default otherwise.
Host Bridge (D0EN): Bus 0, Device 0, Function 0 may
not be disabled and is therefore hardwired to 1.
98
Datasheet