AC82G41SLGQ3 Datasheet, PDF (472/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
Default
Value
RST/PWR
Description
5
RO
Invalidation Completion Error (ICE): Hardware
received an unexpected or invalid Device-IOTLB
invalidation completion. This could be due to either an
invalid ITag or invalid source-ID in an invalidation
completion response. At this time, a fault event may be
generated based on the programming of the Fault Event
0b
Core
Control register.
Hardware implementations not supporting Device-IOTLBs
implement this bit as Reserved.
4
RO
NOTE: This field is reserved as this feature is not
supported.
Invalidation Queue Error (IQE): This field indicates that
hardware detected an error associated with the invalidation
queue. This could be due to either a hardware error while
fetching a descriptor from the invalidation queue, or
hardware detecting an erroneous or invalid descriptor in
the invalidation queue. At this time, a fault event may be
0b
Core
generated based on the programming of the Fault Event
Control register.
Hardware implementations not supporting queued
invalidations implement this bit as Reserved.
3
RO
NOTE: This field is reserved as this feature is not
supported.
Advanced Pending Fault (APF): When this field is Clear,
hardware sets this field when the first fault record (at index
0) is written to a fault log. At this time, a fault event is
generated based on the programming of the Fault Event
Control register.
0b
Core
Software writing 1 to this field clears it. Hardware
implementations not supporting advanced fault logging
implement this bit as Reserved.
NOTE: This field is reserved as this feature is not
supported.
472
Datasheet