AC82G41SLGQ3 Datasheet, PDF (32/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Introduction
1.2.4
1.2.4.1
priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be
specifically enabled and configured at both ends of the DMI link (i.e., the ICH10/ICH7
and (G)MCH).
• A chip-to-chip connection interface to Intel ICH10/ICH7
• 2 GB/s point-to-point DMI to ICH10 (1 GB/s each direction)
• 100 MHz reference clock (shared with PCI Express)
• 32-bit downstream addressing
• APIC and MSI interrupt messaging support. Will send Intel-defined “End Of
Interrupt” broadcast message when initiated by the processor.
• Message Signaled Interrupt (MSI) messages
• SMI, SCI, and SERR error indication
Multiplexed PCI Express* Graphics Interface and Intel^®
sDVO/DVI/HDMI/DP Interface
For the 82Q45, 82Q43, 82B43, 82G45, 82G43, and 82G41 GMCHs, the PCI Express
Interface is multiplexed with the SDVO and HDMI/DVI interfaces. For the 82P45 and
82P43 MCHs, the PCI Express Interface is not multiplexed.
PCI Express* Interface
The (G)MCH supports either two PCI Express* 8-lane (x8) ports or one PCI Express 16-
lane (x16) port.
The (G)MCH contains one 16-lane (x16) PCI Express port intended for supporting up to
two external PCI Express graphics card in bifurcated mode, fully compliant to the PCI
Express Base Specification, Revision 2.0.
• Supports PCI Express GEN1 frequency of 1.25 GHz resulting in 2.5 Gb/s each
direction (500 MB/s total). Maximum theoretical bandwidth on interface of 4 GB/s
in each direction simultaneously, for an aggregate of 8 GB/s when operating in x16
mode.
• Supports PCI Express GEN2 frequency of 2.5 GHz resulting in 5.0 Gb/s each
direction (1000 MB/s total). Maximum theoretical bandwidth on interface of 8 GB/s
in each direction simultaneously, for an aggregate of 16 GB/s when operating in
x16 mode.
• PCI Express port 0 is mapped to PCI Device 1 (PEG).
• PCI Express port 1 is mapped to PCI Device 6 (PEG2).
• Peer to Peer traffic is supported on Virtual Channel 0:
— From DMI to PEG
— From DMI to PEG2
— From PEG to PEG2
— From PEG2 to PEG
• Supports PCI Express Enhanced Access Mechanism. Allowing accesses to the device
configuration space in a flat memory mapped fashion.
• The port may negotiate down to narrower widths. For each of the ports:
— Support for x16/x8/x4/x1 widths for a single PEG mode.
— Support for the x8/x4/x1 widths for a dual PEG mode.
— x1 width support simultaneously with the sDVO functionality which is
multiplexed onto the PEG port. Such shared use facilitates ADD2+/MEC
implementation.
• The x16 lanes can be configured to two ports in bifurcated mode. In this mode,
maximum x8 width is supported.
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Datasheet