AC82G41SLGQ3 Datasheet, PDF (156/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
12
11:10
9:1
0
Access
R/W
RO
R/W
R/W
Default
Value
0b
0h
0000000
00b
0b
RST/PWR
Description
Core
Core
Core
EPDunit Power Down enable for Active Rank
(EPDAAPDEN): This bit enables the active rank to
dynamically enter power down.
1 = Enable active power down.
0 = Disable active power down.
Reserved
Self refresh exit count (sd0_cr_slfrfsh_exit_cnt): This
field indicates the Self refresh exit count. Program to 255.
indicates only 1 rank enabled
(sd0_cr_singledimmpop): This field indicates that only 1
rank is enabled. This bit needs to be set if there is one active
rank and no odt ranks, or if there is one active rank and one
odt rank and they are the same rank.
5.2.40
EPDREFCONFIG—EP DRAM Refresh Configuration
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A30-A33h
40000C30h
RO, R/W
32 bits
Bit
Access
31
RO
30:29
R/W
28
R/W
Default
Value
0b
10b
0b
RST/PWR
Description
Core
Core
Core
Reserved
EPDunit refresh count addition for self refresh exit.
(EPDREF4SR): This field indicates the number of
additional refreshes that needs to be added to the refresh
request count after exiting self refresh.
Typical value is to add 2 refreshes.
00 = Add 0 Refreshes
01 = Add 1 Refreshes
10 = Add 2 Refreshes
11 = Add 3 Refreshes
Refresh Counter Enable (REFCNTEN): This bit is used
to enable the refresh counter to count during times that
DRAM is not in self-refresh, but refreshes are not enabled.
Such a condition may occur due to need to reprogram
DIMMs following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e. there is
no mode where Refresh is enabled but the counter does
not run) So, in conjunction with bit 23 REFEN, the modes
are:
REFEN:REFCNTEN Description
0:0
Normal refresh disable
0:1
Refresh disabled, but counter is
accumulating refreshes.
1:X
Normal refresh enable
156
Datasheet