AC82G41SLGQ3 Datasheet, PDF (128/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.3
C0DRB1—Channel 0 DRAM Rank Boundary Address 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
202-203h
0000h
RO, R/W/L
16 bits
See the C0DRB0 register for detailed descriptions.
Bit
15:10
9:0
5.2.4
Access
RO
R/W/L
Default
Value
000000b
000h
RST/PWR
Description
Core
Core
Reserved
Channel 0 Dram Rank Boundary Address 1
(C0DRBA1): This register defines the DRAM rank
boundary for rank1 of Channel 0 (64 MB granularity)
=(R1 + R0)
R0 = Total rank0 memory size/64 MB
R1 = Total rank1 memory size/64 MB
R2 = Total rank2 memory size/64 MB
R3 = Total rank3 memory size/64 MB
This register is locked by ME stolen Memory lock.
C0DRB2—Channel 0 DRAM Rank Boundary Address 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
204-205h
0000h
RO, R/W/L
16 bits
See the C0DRB0 register for detailed descriptions.
Bit
15:10
9:0
Access
RO
R/W/L
Default
Value
000000b
000h
RST/PWR
Description
Core
Core
Reserved
Channel 0 DRAM Rank Boundary Address 2
(C0DRBA2): This register defines the DRAM rank
boundary for rank2 of Channel 0 (64 MB granularity)
=(R2 + R1 + R0)
R0 = Total rank0 memory size/64 MB
R1 = Total rank1 memory size/64 MB
R2 = Total rank2 memory size/64 MB
R3 = Total rank3 memory size/64 MB
This register is locked by ME stolen Memory lock.
128
Datasheet