AC82G41SLGQ3 Datasheet, PDF (181/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.8
HDR1—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
Eh
01h
RO
8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Bit
7:0
6.1.9
Access
RO
Default
Value
01h
RST/PWR
Description
Core
Header Type Register (HDR): This field returns 01h to
indicate that this is a single function device with bridge
header layout.
PBUSN1—Primary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
18h
00h
RO
8 bits
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus 0.
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
Primary Bus Number (BUSN): Configuration software
typically programs this field with the number of the bus on
00h
Core
the primary side of the bridge. Since device 1 is an internal
device and its primary bus is always 0, these bits are read
only and are hardwired to 0.
6.1.10
SBUSN1—Secondary Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
19h
00h
R/W
8 bits
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge (i.e., to PCI Express). This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express.
Bit
Access
Default
Value
RST/PWR
Description
Secondary Bus Number (BUSN): This field is
7:0
R/W
00h
Core
programmed by configuration software with the bus
number assigned to PCI Express.
Datasheet
181