AC82G41SLGQ3 Datasheet, PDF (366/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.9
IDESNOR1—IDE Sector Number Out Register Device 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
3h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register is read by the Host if DEV = 1. ME-Firmware writes to this register at the
end of a command of the selected device.
When the host writes to the IDE Sector Number In Register (IDESNIR), this register is
updated with that value.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Sector Number Out DEV 1 (IDESNO1): Sector
Number Out register for Slave device.
10.6.10 IDESNIR—IDE Sector Number In Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
3h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Sector Number register of the command block of the IDE
function. This register can be written only by the Host. When host writes to this
register, all 3 registers (IDESNIR, IDESNOR0, IDESNOR1) are updated with the written
value.
Host read to this register address reads the IDE Sector Number Out Register
IDESNOR0 if DEV=0 or IDESNOR1 if DEV=1.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Sector Number Data (IDESND): This register
contains the number of the first sector to be transferred.
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Datasheet