AC82G41SLGQ3 Datasheet, PDF (601/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Testability
Table 56.
JTAG Pins
Pin
JTAG_TCK
Direction
Input
JTAG_TMS
Input with
weak pullup
JTAG_TDI
Input with
weak pullup
JTAG_TDO Output
Description
Test clock pin for JTAG TAP Controller and test logic
JTAG Test Mode Select pin. Sampled by the TAP on the Rising edge
of TCK to control the operation of the TAP state machine. It is
recommended that TMS is held high when (CL_PWROK) is driven
from low-to-high, to ensure deterministic operation of the test
logic.
JTAG Test Data Input pin, sampled on the Rising edge of TCK to
provide serial test instructions and data.
JTAG Test Data Output pin. In inactive drive state except when
instructions or data are being shifted. TDO changes on the falling
edge of TCK. During shifting, TDO drives actively high and low.
Figure 23. JTAG Test Mode Initialization Cycles
TMS
TDI
TCK
T _JC
T _{J SU}
T _JH
T _JCL
T JC O
T JC O
TD O
T _{JC H}
T J VZ
Table 57.
JTAG Signal Timings
Symbol
Parameter
T_JC
T_JCL
T_JCH
T_JSU
T_JH
T_JCO
T_JVZ
JTAG TCK clock period
JTAG TCK clock low time
JTAG TCK clock high time
Setup of TMS and TDI before TCK rising
TMS and TDI hold after TCK rising
TCK falling to TDO output valid
TCK falling to TDO output high-impedance
Min
25
0.4 * T_JC
0.4 * T_JC
11
5
—
—
Max
—
—
—
—
—
7
9
Unit
ns
ns
ns
ns
ns
ns
ns
Notes
40 MHZ
Datasheet
601