AC82G41SLGQ3 Datasheet, PDF (265/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.44
RCTL—Root Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
BC–BDh
0000h
RO, RW
16 bits
This register allows control of PCI Express Root Complex specific parameters. The
system error control bits in this register determine if corresponding SERRs are
generated when our device detects an error (reported in this device's Device Status
register) or when an error message is received across the link. Reporting of SERR as
controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
Bit
15:4
3
2
1
0
Access
RO
RW
RW
RW
RW
Default
Value
000h
0b
0b
0b
0b
RST/
PWR
Core
Core
Core
Core
Core
Description
Reserved
PME Interrupt Enable (PMEIE):
0 = No interrupts are generated as a result of receiving PME
messages.
1 = Enables interrupt generation upon receipt of a PME message as
reflected in the PME Status bit of the Root Status Register. A PME
interrupt is also generated if the PME Status bit of the Root Status
Register is set when this bit is set from a cleared state.
System Error on Fatal Error Enable (SEFEE): This bit controls the
Root Complex's response to fatal errors.
0 = No SERR generated on receipt of fatal error.
1 = Indicates that an SERR should be generated if a fatal error is
reported by any of the devices in the hierarchy associated with
this Root Port, or by the Root Port itself.
System Error on Non-Fatal Uncorrectable Error Enable
(SENFUEE): This bit controls the Root Complex's response to non-
fatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = Indicates that an SERR should be generated if a non-fatal error is
reported by any of the devices in the hierarchy associated with
this Root Port, or by the Root Port itself.
System Error on Correctable Error Enable (SECEE): This bit
controls the Root Complex's response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = Indicates that an SERR should be generated if a correctable error
is reported by any of the devices in the hierarchy associated with
this Root Port, or by the Root Port itself.
Datasheet
265