AC82G41SLGQ3 Datasheet, PDF (453/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.1.19 IVA_REG—Invalidate Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/VC0PREMAP
100-107h
0000000000000000h
W, RO
64 bits
This register provides the DMA address whose corresponding IOTLB entry needs to be
invalidated through the corresponding IOTLB Invalidate register. This register is a write
only register. The value returned on reads of this register is undefined. There is an
IVA_REG for each IOTLB Invalidation unit supported by hardware.
Bit
63:12
11:7
6
Access
W
RO
W
Default
Value
000000000
0000h
00h
0h
RST/PWR
Description
Core
Core
Core
Address (Addr): Software provides the DMA address that
needs to be page-selectively invalidated. To request a
page-selective invalidation request to hardware, software
must first write the appropriate fields in this register, and
then issue appropriate page-selective invalidate command
through the IOTLB_REG.
Hardware ignores bits 63:N, where N is the maximum
guest address width (MGAW) supported.
Value returned on read of this field is undefined.
Reserved
Invalidation Hint (IH): The field provides hints to
hardware to preserve or flush the non-leaf (page-
directory) entries that may be cached in hardware.
0 = Software may have modified both leaf and non-leaf
page-table entries corresponding to mappings
specified in the ADDR and AM fields. On a
pageselective invalidation request, hardware must
flush both the cached leaf and non-leaf page-table
Value returned on read of this field is undefined.
entries corresponding to mappings specified by ADDR
and AM fields.
1 = Software has not modified any non-leaf page-table
entries corresponding to mappings specified in the
ADDR and AM fields. On a page-selective invalidation
request, hardware may preserve the cached non-leaf
page-table entries corresponding to mappings
specified by ADDR and AM fields.
Datasheet
453