AC82G41SLGQ3 Datasheet, PDF (178/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.4
PCISTS1—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
6-7h
0010h
RO, R/WC
16 bits
This register reports the occurrence of error conditions associated with primary side of
the "virtual" Host-PCI Express bridge embedded within the (G)MCH.
Bit
15
14
13
12
11
10:9
8
7
6
5
Access
RO
R/WC
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
00b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Detected Parity Error (DPE): Not Applicable or
Implemented. Hardwired to 0. Parity (generating poisoned
TLPs) is not supported on the primary side of this device.
Error forwarding is not performed.
Signaled System Error (SSE): This bit is set when this
Device sends an SERR due to detecting an ERR_FATAL or
ERR_NONFATAL condition and the SERR Enable bit in the
Command register is 1. Both received (if enabled by
BCTRL1[1]) and internally detected error messages do not
affect this field.
Received Master Abort Status (RMAS): Not Applicable
or Implemented. Hardwired to 0. The concept of a master
abort does not exist on primary side of this device.
Received Target Abort Status (RTAS): Not Applicable
or Implemented. Hardwired to 0. The concept of a target
abort does not exist on primary side of this device.
Signaled Target Abort Status (STAS): Not Applicable or
Implemented. Hardwired to 0. The concept of a target
abort does not exist on primary side of this device.
DEVSELB Timing (DEVT): This device is not the
subtractive decode device on bus 0. This bit field is
therefore hardwired to 00 to indicate that the device uses
the fastest possible decode.
Master Data Parity Error (PMDPE): Because the
primary side of the PEG's virtual PCI-to-PCI bridge is
integrated with the MCH functionality there is no scenario
where this bit will get set. Because hardware will never set
this bit, it is impossible for software to have an opportunity
to clear this bit or otherwise test that it is implemented.
The PCI specification defines it as a R/WC, but for our
implementation an RO definition behaves the same way
and will meet all Microsoft testing requirements.
This bit can only be set when the Parity Error Enable bit in
the PCI Command register is set.
Fast Back-to-Back (FB2B): Not Applicable or
Implemented. Hardwired to 0.
Reserved
66/60MHz capability (CAP66): Not Applicable or
Implemented. Hardwired to 0.
178
Datasheet