AC82G41SLGQ3 Datasheet, PDF (192/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
Bit
Access
Default
Value
RST/PWR
Description
ISA Enable (ISAEN): This bit is needed to exclude legacy
resource decode to route ISA resources to legacy decode
path. Modifies the response by the (G)MCH to an I/O
access issued by the processor that target ISA I/O
addresses. This applies only to I/O addresses that are
enabled by the IOBASE and IOLIMIT registers.
2
R/W
0b
Core
0 = All addresses defined by the IOBASE and IOLIMIT for
processor I/O transactions will be mapped to PCI
Express.
1 = (G)MCH will not forward to PCI Express any I/O
transactions addressing the last 768 bytes in each
1 KB block even if the addresses are within the range
defined by the IOBASE and IOLIMIT registers.
SERR Enable (SERREN):
0 = No forwarding of error messages from secondary side
1
R/W
0b
Core
to primary side that could result in an SERR.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages
result in SERR message when individually enabled by
the Root Control register.
Parity Error Response Enable (PEREN): This bit
controls whether or not the Master Data Parity Error bit in
the Secondary Status register is set when the MCH
receives across the link (upstream) a Read Data
0
R/W
0b
Core
Completion Poisoned TLP.
0 = Master Data Parity Error bit in Secondary Status
register can NOT be set.
1 = Master Data Parity Error bit in Secondary Status
register CAN be set.
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Datasheet