AC82G41SLGQ3 Datasheet, PDF (367/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.11 IDECLIR—IDE Cylinder Low In Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
4h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Cylinder Low register of the command block of the IDE
function. This register can be written only by the Host. When host writes to this
register, all 3 registers (IDECLIR, IDECLOR0, IDECLOR1) are updated with the written
value.
Host read to this register address reads the IDE Cylinder Low Out Register IDECLOR0 if
DEV=0 or IDECLOR1 if DEV=1.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Cylinder Low Data (IDECLD): Cylinder Low register
of the command block of the IDE function.
10.6.12 IDCLOR1—IDE Cylinder Low Out Register Device 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
4h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register is read by the Host if DEV = 1. ME-Firmware writes to this register at the
end of a command of the selected device. When the host writes to the IDE Cylinder Low
In Register (IDECLIR), this register is updated with that value.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Cylinder Low Out DEV 1. (IDECLO1): Cylinder Low
Out Register for Slave Device.
Datasheet
367