AC82G41SLGQ3 Datasheet, PDF (479/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.2.15 PLMBASE_REG—Protected Low-Memory Base Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
68-6Bh
00000000h
R/W, RO
32 bits
This register is used to setup the base address of DMA protected low-memory region.
This register must be setup before enabling protected memory through PMEN_REG,
and must not be updated when protected memory regions are enabled. When
LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO). When
LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated as R/W).
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as 0 in the Capability register). The alignment of
the protected low memory region base depends on the number of reserved bits (N) of
this register. Software may determine the value of N by writing all 1s to this register,
and finding most significant zero bit position with 0 in the value read back from the
register. Bits N:0 of this register is decoded by hardware as all 0s.
Bit
31:21
20:0
Access
R/W
RO
Default
Value
000h
000000h
RST/PWR
Description
Core
Core
Protected Low-Memory Base (PLMB): This register
specifies the base of size aligned, protected low-memory
region in system memory. The protected low-memory
region has a minimum size of 2 MB and must be size
aligned.
Reserved
Datasheet
479