AC82G41SLGQ3 Datasheet, PDF (259/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.40
LSTS—Link Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
B2–B3h
1000h
RWC, RO
16 bits
This register indicates PCI Express link status.
Bit
Access
Default
Value
RST/
PWR
Description
15
RWC
Link Autonomous Bandwidth Status (LABWS): This bit is set to
1b by hardware to indicate that hardware has autonomously changed
link speed or width, without the port transitioning through DL_Down
status, for reasons other than to attempt to correct unreliable link
0b
Core _operation.
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was
indicated as an autonomous change.
Link Bandwidth Management Status (LBWMS): This bit is set to
1b by hardware to indicate that either of the following has occurred
without the port transitioning through DL_Down status:
A link retraining initiated by a write of 1b to the Retrain Link bit has
completed.
14
RWC
13
RO
12
RO
11
RO
NOTE: This bit is Set following any write of 1b to the Retrain Link bit,
0b
Core
including when the Link is in the process of retraining for some
other reason.
Hardware has autonomously changed link speed or width to attempt
to correct unreliable link operation, either through an LTSSM timeout
or a higher level process
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was not
indicated as an autonomous change.
Data Link Layer Link Active (Optional) (DLLLA): This bit
indicates the status of the Data Link Control and Management State
Machine. It returns a 1b to indicate the DL_Active state, 0b
0b
Core ^otherwise.
This bit must be implemented if the corresponding Data Link Layer
Active Capability bit is implemented. Otherwise, this bit must be
hardwired to 0b.
Slot Clock Configuration (SCC):
0 = The device uses an independent clock irrespective of the
1b
Core
presence of a reference on the connector.
1 = The device uses the same physical reference clock that the
platform provides on the connector.
Link Training (LTRN): This bit indicates that the Physical Layer
LTSSM is in the Configuration or Recovery state, or that 1b was
0b
Core written to the Retrain Link bit but Link training has not yet begun.
Hardware clears this bit when the LTSSM exits the Configuration/
Recovery state once Link training is complete.
Datasheet
259