AC82G41SLGQ3 Datasheet, PDF (373/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.21 IDESD1R—IDE Status Device 1 Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
7h
80h
R/W/V
8 bits
Reset: Host system reset or D3->D0 transition
This register implements the status register of the slave device (DEV = 1). This register
is read only by the Host. Host read of this register clears the slave device's interrupt.
When the HOST writes to the same address it writes to the command register.
The bits description is for ATA mode.
Bit
Access
Default
Value
RST/PWR
Description
7
R/W/V
1b
6
R/W/V
0b
5
R/W/V
0b
4
R/W/V
0b
3
R/W/V
0b
2
R/W/V
0b
1
R/W/V
0b
0
R/W/V
0b
Core
Core
Core
Core
Core
Core
Core
Core
Busy (BSY): This bit is set by hardware when the IDECR
is being written and DEV=0, or when SRST bit is asserted
by the Host or host system reset or D3-to-D0 transition of
the IDE function.
This bit is cleared by FW write of 0.
Drive Ready (DRDY): When set, indicates drive is ready
for command.
Drive Fault (DF): Indicates Error on the drive.
Drive Seek Complete (DSC): Indicates Heads are
positioned over the desired cylinder.
Data Request (DRQ): Set when the drive wants to
exchange data with the Host via the data register.
Corrected Data (CORR): When set indicates a
correctable read error has occurred.
Index (IDX): This bit is set once per rotation of the
medium when the index mark passes under the read/write
head.
Error (ERR): When set, this bit indicates an error
occurred in the process of executing the previous
command. The Error Register of the selected device
contains the error information
Datasheet
373