AC82G41SLGQ3 Datasheet, PDF (346/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
Bit
Access
Default
Value
RST/PWR
Description
2
R/W
0b
1
R/WC
0b
0
R/W
0b
Core
Core
Core
Host Interrupt Generate (H_IG): Once message(s) are
written into its CB, the host sets this bit to 1 for the
hardware to set the ME_IS bit in the ME_CSR and to
generate an interrupt message to ME. Hardware will send
the interrupt message to ME only if the ME_IE is enabled.
Hardware then clears this bit to 0.
Host Interrupt Status (H_IS): Hardware sets this bit to
1 when ME_IG bit is set to 1. Host clears this bit to 0 by
writing a 1 to this bit position. H_IE has no effect on this
bit.
Host Interrupt Enable (H_IE): The Host sets this bit to
1 to enable the host interrupt (INTR# or MSI) to be
asserted when H_IS is set to 1.
10.4.3
ME_CB_RW— ME Circular Buffer Read Window
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/1/MMIO
8-Bh
FFFFFFFFh
RO
32 bits
This register is for host to read from the ME Circular Buffer (ME_CB). The ME's circular
buffer is located at the ME subsystem address specified in the ME CB Base Address
register.
Bit
31:0
Access
RO
Default
Value
FFFFFFFFh
RST/PWR
Description
Core
ME Circular Buffer Read Window Field
(ME_CB_RWF): This bit field is for host to read from the
ME Circular Buffer. The ME's circular buffer is located at the
ME subsystem address specified in the ME CB Base
Address register. This field is read only, writes have no
effect. Reads to this register will increment the ME_CBRP
as long as ME_RDY is 1. When ME_RDY is 0, reads to this
register have no effect, all 1s are returned, and ME_CBRP
is not incremented.
346
Datasheet