AC82G41SLGQ3 Datasheet, PDF (477/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.2.13 AFLOG_REG—Advanced Fault Log Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
58-5Fh
0000000000000000h
RO
64 bits
This register specifies the base address of memory-resident fault-log region. This
register is treated as read only (0) for implementations not supporting advanced
translation fault logging (AFL field reported as 0 in the Capability register). This register
is sticky and can be cleared only through powergood reset or via software clearing the
RW1C fields by writing a 1.
Bit
63:12
11:9
8:0
Access
RO
RO
RO
Default
Value
000000000
0000h
RST/PWR
Description
Core
Fault Log Address (FLA): This field specifies the base of
size-aligned fault-log region in system memory. Hardware
may ignore and not implement bits 63:HAW, where HAW is
the host address width.
Software specifies the base address and size of the fault
log region through this register, and programs it in
hardware through the SFL field in the Global Command
register.
When implemented, reads of this field returns value that
was last programmed to it.
NOTE: This field is reserved as this feature is not
supported.
Fault Log Size (FLS): This field specifies the size of the
fault log region pointed by the FLA field.
00 = 4 KB
01 = 8 KB
10 = 16 KB
0h
Core
11 = 32 KB
When implemented, reads of this field returns value that
was last programmed to it.
NOTE: This field is reserved as this feature is not
supported.
00h
Core
Reserved
Datasheet
477