AC82G41SLGQ3 Datasheet, PDF (551/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Functional Description
13.10.3 Chipset State Combinations
(G)MCH supports the state combinations listed in the Table 44.
Table 44.
G, S, and C State Combinations
Global
Sleep Processor
(G) State (S) State (C) State
Processor
State
G0
S0
C0
Full On
G0
S0
C1
Auto-Halt
G0
S0
C2
Stop Grant
G1
S0
C3
Deep Sleep,
Clock to
processor
Stopped
G1
S0
C4
Deeper Sleep
Reduced
voltage on the
processor
G1
S3
power-off
—
G1
S4
power-off
—
G2
S5
power-off
—
G3
NA
power-off
—
System Clocks
Description
On
Full On
On
Auto Halt
On
Stop Grant
On
Deep Sleep
Deep Sleep with
On
processor voltage
lowered.
Off, except RTC
Off, except RTC
Off, except RTC
power-off
Suspend to RAM
Suspend to Disk
Soft Off
Hard Off
Table 45.
Interface Activity to State Mapping
ACPI
State/
C0/C1/C2
C3/C4
S1
Feature
S3
S4, S5
DRAM
On
(with power
saving
features)
Self-refresh
(with this
power saving
feature
enabled)
On
(with power
saving
features)
Self-refresh for
non-ME
channel.
Other channel is
ME state
dependent
Depending
on ME state
No
No
No
GTL Control,
Data,
Dynamic
Dynamic
Dynamic
Address
disabling of
disabling of
disabling of
Buffer
data bus
data bus
data bus sense On
Sense Amp
Disable
sense amps,
dynamic
transmit clock
sense amps,
dynamic
transmit clock
amps, dynamic
transmit clock
gating
gating
gating
Auto Halt
PCI Express ^L0/L1
State
(ASPM)
L0/L1
(ASPM)
L0/L1
(ASPM)
Power Off
Power Off
DMI
Interface
L0/L1
(ASPM)
L0/L1
(ASPM)
L0/L1
(ASPM
Power Off
Power Off
HPLL
Running
Running
Running
Depending on
ME State
Depending
on ME State
Datasheet
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