AC82G41SLGQ3 Datasheet, PDF (448/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.1.14 PMEN_REG—Protected Memory Enable Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/VC0PREMAP
64-67h
00000000h
RO, R/W
32 bits
This register is used to enable the DMA protected memory regions setup through the
PLMBASE, PLMLIMT, PHMBASE, PHMLIMIT registers. When LT.CMD.LOCK.PMRC
command is invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC
command is invoked, this register is unlocked (treated as R/W). This register is always
treated as RO (0) for implementations not supporting protected memory regions (PLMR
and PHMR fields reported as 0 in the Capability register).
Bit
31
30:1
0
Access
R/W
RO
RO
Default
Value
0h
00000000h
0h
RST/PWR
Description
Core
Core
Core
Enable Protected Memory (EPM): This field controls
DMA accesses to the protected low-memory and protected
high-memory regions.
0 = DMA accesses to protected memory regions are
handled as follows:
— If DMA-remapping hardware is not enabled, DMA
requests (including those to protected regions) are
not blocked.
— If DMA-remapping hardware is enabled, DMA
requests are translated per the programming of the
DMA-remapping structures. Software may program
the DMA-remapping structures to allow or block
DMA to the protected memory regions.
1 = DMA accesses to protected memory regions are
handled as follows:
— If DMA-remapping hardware is not enabled, DMA to
protected memory regions are blocked. These DMA
requests are not recorded or reported as DMA-
remapping faults.
— If DMA-remapping hardware is enabled, hardware
may or may not block DMA to the protected
memory region(s). Software must not depend on
hardware protection of the protected memory
regions, and must ensure the DMA-remapping
structures are properly programmed to not allow
DMA to the protected memory regions.
Hardware reports the status of the protected memory
enable/disable operation through the PRS field in this
register.
Hardware implementations supporting DMA draining must
drain any in-flight translated DMA requests queued within
the root complex before indicating the protected memory
region as enabled through the PRS field.
Reserved
Protected Region Status (PRS): This field indicates the
status of protected memory region.
0 = Protected memory region(s) not enabled.
1 = Protected memory region(s) enabled.
448
Datasheet