AC82G41SLGQ3 Datasheet, PDF (315/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10 Intel^® Manageability Engine
Subsystem Registers
10.1 HECI Function in ME subsystem Registers
Table 17.
HECI Function in ME Subsystem Register Address Map
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
0–3h
4–5h
6–7h
8h
9–Bh
Ch
Dh
Eh
Fh
10–17h
2C–2Fh
34h
3C–3Dh
3Eh
3F
40–43h
50–51h
52–53h
54–55h
8C–8Dh
8E–8Fh
90–93h
94–97h
98–99h
ID
CMD
STS
Identifiers
Command
Device Status
RID
Revision ID
CC
CLS
MLT
HTYPE
BIST
Class Code
Cache Line Size
Master Latency Timer
Header Type
Built In Self Test
HECI_MBAR HECI MMIO Base Address
SS
CAP
INTR
MGNT
MLAT
HFS
PID
PC
PMCS
MID
MC
MA
MUA
MD
Sub System Identifiers
Capabilities Pointer
Interrupt Information
Minimum Grant
Maximum Latency
Host Firmware Status
PCI Power Management Capability ID
PCI Power Management Capabilities
PCI Power Management Control And
Status
Message Signaled Interrupt
Identifiers
Message Signaled Interrupt Message
Control
Message Signaled Interrupt Message
Address
Message Signaled Interrupt Upper
Address (Optional)
Message Signaled Interrupt Message
Data
2E048086h
0000h
0010h
see
description
0C8001h
00h
00h
80h
00h
0000000000
000004h
00000000h
50h
0100h
00h
00h
00000000h
8C01h
C803h
0008h
0005h
0080h
00000000h
00000000h
0000h
RO
RO, R/W
RO
RO
RO
RO
RO
RO
RO
RO, R/W
R/WO
RO
RO, R/W
RO
RO
RO
RO
RO
R/WC, RO,
R/W
RO
RO, R/W
R/W, RO
R/W
R/W
Datasheet
315