AC82G41SLGQ3 Datasheet, PDF (176/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.3
PCICMD1—PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
4-5h
0000h
RO, R/W
16 bits
Bit
15:11
Access
RO
10
R/W
9
RO
8
R/W
7
RO
6
R/W
Default
Value
00h
0b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Reserved
INTA Assertion Disable (INTAAD):
0 = This device is permitted to generate INTA interrupt
messages.
1 = This device is prevented from generating interrupt
messages. Any INTA emulation interrupts already
asserted must be de-asserted when this bit is set.
Only affects interrupts generated by the device (PCI INTA
from a PME or Hot Plug event) controlled by this command
register. It does not affect upstream MSIs, upstream PCI
INTA–INTD assert and de-assert messages.
Fast Back-to-Back Enable (FB2B): Not Applicable or
Implemented. Hardwired to 0.
SERR# Message Enable (SERRE1): This bit controls
Device 1 SERR# messaging. The (G)MCH communicates
the SERR# condition by sending a SERR message to the
ICH. This bit, when set, enables reporting of non-fatal and
fatal errors detected by the device to the Root Complex.
Note that errors are reported if enabled either through this
bit or through the PCI-Express specific bits in the Device
Control Register.
In addition, for Type 1 configuration space header devices,
this bit, when set, enables transmission by the primary
interface of ERR_NONFATAL and ERR_FATAL error
messages forwarded from the secondary interface. This bit
does not affect the transmission of forwarded ERR_COR
messages.
0 = The SERR message is generated by the (G)MCH for
Device 1 only under conditions enabled individually
through the Device Control Register.
1 = The (G)MCH is enabled to generate SERR messages,
which will be sent to the ICH for specific Device 1
error conditions generated/detected on the primary
side of the virtual PCI to PCI bridge (not those
received by the secondary side). The status of SERRs
generated is reported in the PCISTS1 register.
Reserved: Not Applicable or Implemented. Hardwired to 0.
Parity Error Response Enable (PERRE): This bit
controls whether or not the Master Data Parity Error bit in
the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can
NOT be set.
1 = Master Data Parity Error bit in PCI Status register CAN
be set.
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Datasheet