AC82G41SLGQ3 Datasheet, PDF (247/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.24 BCTRL1—Bridge Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/PCI
3E–3Fh
0000h
RO, RW
16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface as well as
some bits that affect the overall behavior of the "virtual" Host-PCI Express bridge
embedded in the MCH.
Bit
Access
Default
Value
15:12 RO
0h
11
RO
0b
10
RO
0b
9
RO
0b
8
RO
0b
7
RO
0b
6
RW
0b
5
RO
0b
4
RW
0b
3
RW
0b
2
RW
0b
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Core
Description
Reserved
Discard Timer SERR# Enable (DTSERRE): Not Applicable or
Implemented. Hardwired to 0.
Discard Timer Status (DTSTS): Not Applicable or Implemented.
Hardwired to 0.
Secondary Discard Timer (SDT): Not Applicable or Implemented.
Hardwired to 0.
Primary Discard Timer (PDT): Not Applicable or Implemented.
Hardwired to 0.
Fast Back-to-Back Enable (FB2BEN): Not Applicable or Implemented.
Hardwired to 0.
Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset on
the corresponding PCI Express Port. This will force the LTSSM to transition
to the Hot Reset state (via Recovery) from L0 or L1 states.
Master Abort Mode (MAMODE): Does not apply to PCI Express.
Hardwired to 0.
VGA 16-bit Decode (VGA16D): Enables the PCI-to-PCI bridge to
provide 16-bit decoding of VGA I/O address precluding the decoding of
alias addresses every 1 KB. This bit only has meaning if bit 3 (VGA Enable)
of this register is also set to 1, enabling VGA I/O decoding and forwarding
by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
VGA Enable (VGAEN): Controls the routing of processor initiated
transactions targeting VGA compatible I/O and memory address ranges.
See the VGAEN/MDAP table in device 0, offset 97h[0].
ISA Enable (ISAEN): Needed to exclude legacy resource decode to route
ISA resources to legacy decode path. Modifies the response by the MCH to
an I/O access issued by the processor that target ISA I/O addresses. This
applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT
registers.
0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions will be mapped to PCI Express.
1 = MCH will not forward to PCI Express any I/O transactions addressing
the last 768 bytes in each 1 KB block even if the addresses are within
the range defined by the IOBASE and IOLIMIT registers.
Datasheet
247