AC82G41SLGQ3 Datasheet, PDF (405/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.10.9 KTMCR—KT Modem Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
4h
00h
RO, R/W
8 bits
Reset: Host system Reset or D3->D0 transition.
The Modem Control Register controls the interface with the modem. Since the FW
emulates the modem, the Host communicates to the FW via this register. Register has
impact on hardware when the Loopback mode is on.
Bit
Access
Default
Value
RST/PWR
Description
7:5
RO
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
000b
0b
0b
0b
0b
0b
Core
Core
Core
Core
Core
Core
Reserved
Loop Back Mode (LBM): When set by the Host, this bit
indicates that the serial port is in loop Back mode. This
means that the data that is transmitted by the host should
be received. Helps in debug of the interface.
Output 2 (OUT2): This bit has no affect on hardware in
normal mode. In loop back mode the value of this bit is
written by hardware to the Modem Status Register bit 7.
Output 1 (OUT1): This bit has no affect on hardware in
normal mode. In loop back mode the value of this bit is
written by hardware to Modem Status Register bit 6.
Request to Send Out (RTSO): This bit has no affect on
hardware in normal mode. In loopback mode, the value of
this bit is written by hardware to Modem Status Register
bit 4.
Data Terminal Ready Out (DRTO): This bit has no affect
on hardware in normal mode. In loopback mode, the value
in this bit is written by hardware to Modem Status Register
Bit 5.
Datasheet
405