AC82G41SLGQ3 Datasheet, PDF (180/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.6
CC1—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
9-Bh
060400h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a
register- specific programming interface.
Bit
23:16
15:8
7:0
6.1.7
Access
RO
RO
RO
Default
Value
06h
04h
00h
RST/PWR
Description
Core
Core
Core
Base Class Code (BCC): This field indicates the base
class code for this device.
06h = Bridge device.
Sub-Class Code (SUBCC): This field indicates the sub-
class code for this device.
04h = PCI-to-PCI Bridge.
Programming Interface (PI): This field indicates the
programming interface of this device. This value does not
specify a particular register set layout and provides no
practical use for this device.
CL1—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
Ch
00h
R/W
8 bits
Bit
Access
Default
Value
RST/PWR
Description
Cache Line Size (Scratch pad): This field is
7:0
R/W
00h
Core
implemented by PCI Express devices as a read-write field
for legacy compatibility purposes but has no impact on any
PCI Express device functionality.
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Datasheet