AC82G41SLGQ3 Datasheet, PDF (111/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.26
REMAPBASE—Remap Base Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
98-99h
03FFh
RO, R/W/L
16 bits
Bit
15:10
9:0
Access
RO
R/W/L
Default
Value
000000b
3FFh
RST/PWR
Description
Core
Core
Reserved
Remap Base Address [35:26] (REMAPBASE): The
value in this register defines the lower boundary of the
Remap window. The Remap window is inclusive of this
address. In the decoder A[25:0] of the Remap Base
Address are assumed to be 0s. Thus the bottom of the
defined memory range will be aligned to a 64 MB
boundary.
When the value in this register is greater than the value
programmed into the Remap Limit register, the Remap
window is disabled.
These bits are Intel TXT lockable (82Q45/82Q43 GMCH
only) or ME stolen Memory lockable.
5.1.27
REMAPLIMIT—Remap Limit Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
9A-9Bh
0000h
RO, R/W/L
16 bits
Bit
15:10
9:0
Access
RO
R/W/L
Default
Value
000000b
000h
RST/PWR
Description
Core
Core
Reserved
Remap Limit Address [35:26] (REMAPLMT): The value
in this register defines the upper boundary of the Remap
window. The Remap window is inclusive of this address. In
the decoder A[25:0] of the remap limit address are
assumed to be Fh. Thus the top of the defined range will be
one less than a 64 MB boundary.
When the value in this register is less than the value
programmed into the Remap Base register, the Remap
window is disabled.
These Bits are Intel TXT lockable (82Q45/82Q43 GMCH
only) or ME stolen Memory lockable.
Datasheet
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