AC82G41SLGQ3 Datasheet, PDF (286/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.17
INTRLINE—Interrupt Line
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
3Ch
00h
R/W
8 bits
Bit
Access
Default
Value
RST/PWR
Description
Interrupt Connection (INTCON): This field is used to
communicate interrupt line routing information. POST
7:0
R/W
00h
Core
software writes the routing information into this register as
it initializes and configures the system. The value in this
register indicates to which input of the system interrupt
controller the device's interrupt pin is connected.
9.1.18
INTRPIN—Interrupt Pin
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
3Dh
01h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
Interrupt Pin (INTPIN): As a single function device, the
01h
Core
IGD specifies INTA# as its interrupt pin.
01h = INTA#.
9.1.19
MINGNT—Minimum Grant
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
3Eh
00h
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
00h
Core
Minimum Grant Value (MGV): The IGD does not burst
as a PCI compliant master.
286
Datasheet