AC82G41SLGQ3 Datasheet, PDF (343/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.3.4
ME_CSR_HA— ME Control Status Host Access
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/MMIO
C-Fh
02000000h
RO
32 bits
This register allows host software to read the ME Control Status register (ME_CSR).
This register is reset by MERST#.
Bit
31:24
23:16
15:8
7:5
4
3
2
1
0
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
02h
00h
00h
000b
0b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
ME Circular Buffer Depth Host Read Access
(ME_CBD_HRA): Host read only access to ME_CBD.
ME CB Write Pointer Host Read Access
(ME_CBWP_HRA): Host read only access to ME_CBWP.
ME CB Read Pointer Host Read Access
(ME_CBRP_HRA): Host read only access to ME_CBRP.
Reserved
ME Reset Host Read Access (ME_RST_HRA): Host
read access to ME_RST.
ME Ready Host Read Access (ME_RDY_HRA): Host
read access to ME_RDY.
ME Interrupt Generate Host Read Access
(ME_IG_HRA): Host read only access to ME_IG.
ME Interrupt Status Host Read Access (ME_IS_HRA):
Host read only access to ME_IS.
ME Interrupt Enable Host Read Access
(ME_IE_HRA): Host read only access to ME_IE.
Datasheet
343