AC82G41SLGQ3 Datasheet, PDF (540/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Functional Description
13.5.2.7 Multiplexed Digital Display Channels –
Intel^® SDVOB and Intel^® SDVOC
The GMCH supports digital display devices through two SDVO ports multiplexed with
the PEG signals. When an external graphics accelerator is used via the PEG port, these
SDVO ports are not available.
The shared SDVO ports each support a pixel clock up to 200 MHz and can support a
variety of transmission devices.
SDVO_CTRLDATA is an open-drain signal that acts as a strap during reset to tell the
GMCH whether the interface is a PCI Express interface or an SDVO interface. When
implementing SDVO, either using ADD2 cards or with a down device, a pull-up resistor
is placed on this line to signal to the GMCH to run in SDVO mode and for proper GMBus
operation.
13.5.2.7.1 ADD2/MEDIA EXPANSION CARD(MEC)
When a PEG connector is used in the platform, the multiplexed SDVO ports may be
used via an ADD2 or MEC card. The ADD2 card will be designed to fit a standard PCI
Express (x16) connector.
Figure 13. Display configurations on ATX Platforms
(G)MCH
PEG
Signals
(G)MCH
PEG
Pins
0
0
0
X1 PCIe
Card
ATX Form Factor
0
X4 SDVO
ADD2/+
Card
PCIe Lane 3
0
Digital Port
B
HDMI/DP/DVI
PCIe Lane 3
0
X1 PCIe
MEC Card
X16 PCIe
Card
X8 SDVO
(ADD2/+)
Card
PCIe Lane 7
Digital Port
C
HDMI/DP/DVI
PCIe Lane 7
PCIe Lane 8
SDVO/Digital
Port C
PCIe Lane 11
15
15
SDVO/Digital
Port B
15
15
15
PCIe Lane 15 15
SDVO Card
ADD card
Concurrency
Mode
ADD2+/MEC
Card
540
Datasheet