AC82G41SLGQ3 Datasheet, PDF (356/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.5.16 INTR—Interrupt Information
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
3C-3Dh
0300h
R/W, RO
16 bits
Reset: Host System Reset or D3->D0 reset of the function
See definitions in the registers below
Bit
15:8
7:0
Access
RO
R/W
Default
Value
03h
00h
RST/PWR
Description
Core
Core
Interrupt Pin (IPIN): A value of 0x1/0x2/0x3/0x4
indicates that this function implements legacy interrupt on
INTA/INTB/INTC/INTD, respectively
Function Value INTx
(2 IDE) 03h
INTC
Interrupt Line (ILINE): The value written in this register
indicates which input of the system interrupt controller, the
device's interrupt pin is connected to. This value is used by
the OS and the device driver, and has no affect on the
hardware.
10.5.17 MGNT—Minimum Grant
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
3Eh
00h
RO
8 bits
This optional register is not implemented.
Bit
Access
Default
Value
RST/PWR
7:0
RO
00h
Core
Reserved
10.5.18 MLAT—Maximum Latency
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
3Fh
00h
RO
8 bits
This optional register is not implemented.
Description
Bit
Access
Default
Value
RST/PWR
7:0
RO
00h
Core
Reserved
Description
356
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